{"id":6720,"date":"2020-04-03T15:37:29","date_gmt":"2020-04-03T10:07:29","guid":{"rendered":"https:\/\/nuclearrambo.com\/wordpress\/?p=6720"},"modified":"2024-10-03T15:19:01","modified_gmt":"2024-10-03T09:49:01","slug":"programming-the-zynq-7000-with-vivado-2019-2-and-vitis","status":"publish","type":"post","link":"https:\/\/nuclearrambo.com\/wordpress\/programming-the-zynq-7000-with-vivado-2019-2-and-vitis\/","title":{"rendered":"Programming the Zynq 7000 with Vivado 2019.2 and Vitis"},"content":{"rendered":"\n<p>I purchased a Zynq 7000 development board recently and wanted to play with it for quite some time now. Finally, the lock-down due to the corona virus pandemic gave me some time to put my hands on <a href=\"https:\/\/amzn.to\/3vfGB15\" target=\"_blank\" rel=\"noopener nofollow noreferrer\">Zynq SoC development<\/a>. In the past, I had spent most of my time developing RTL code for various projects. Ever since Zynq SoC had come out on the market, it had interested me mainly because of the tight integration of the programmable logic and the dual core ARM applications processor. The combination of the two has lead to integration of so many system components in various projects out there.<\/p>\n\n\n\n<p>The best example I know in front of me is the <a href=\"https:\/\/amzn.to\/2QwKtft\" target=\"_blank\" rel=\"noopener nofollow noreferrer\">GW Instek GDS-1102, GDS-1104 series of oscilloscopes<\/a>. The entire oscilloscope has its brain embedded into a single Zynq SoC. The processing system handles the display related and user facing side of the things. On the other hand, the programmable logic interfaces with the high speed ADC and does all sort of digital processing you would expect an oscilloscope to do. If you wish to know more, head out to the <a href=\"https:\/\/www.youtube.com\/watch?v=9SXZk2tsQ4g\" target=\"_blank\" rel=\"noopener nofollow noreferrer\">EEVBlog video where Dave tears down<\/a> one of the GW Instek oscilloscopes and explains everything very clearly.<\/p>\n\n\n\n<p>Do not expect a very complicated design in this post. I have saved something good for a later date.<\/p>\n\n\n\n<center><script type=\"text\/javascript\"><br \/>\n\tatOptions = {<br \/>\n\t\t'key' : 'a488f095e80c8a74746e5fdca977eaea',<br \/>\n\t\t'format' : 'iframe',<br \/>\n\t\t'height' : 90,<br \/>\n\t\t'width' : 728,<br \/>\n\t\t'params' : {}<br \/>\n\t};<br \/>\n\tdocument.write('<scr' + 'ipt type=\"text\/javascript\" src=\"http' + (location.protocol === 'https:' ? 's' : '') + ':\/\/www.profitabledisplaynetwork.com\/a488f095e80c8a74746e5fdca977eaea\/invoke.js\"><\/scr' + 'ipt>');<br \/>\n<\/script><\/center>\n\n\n\n<h2 class=\"wp-block-heading\">Block design<\/h2>\n\n\n\n<p>Consider this as a project 0 for someone who wishes to start with Vitis. A lot of projects out there related to Zynq use quite older version of Vivado and SDK. Although, most of the things remain the same, there may be a few changes here and there.<\/p>\n\n\n\n<p>In this very simple project, I will interface 4 LEDs and 4 switches to the Zynq Processing system. The interface would be standard AXI4 because that is the only way you can interface programmable logic to the ARM processor.<\/p>\n\n\n\n<p>It would take me ages to make a tutorial explaining every small step in the GUI. Instead, I am providing you with the tcl script that you can run and make life easy.<\/p>\n\n\n\n<p>First, create project, select the right board and then create a new block design. Make sure you run this all in the Vivado tcl console. Also make sure you change the project according to your need.<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">start_gui\ncreate_project blinky J:\/XilinxProjects\/blinky -part xc7z010clg400-1\nset_property board_part digilentinc.com:zybo:part0:2.0 [current_project]\nset_property target_language VHDL [current_project]<\/pre>\n\n\n\n<p>Now, add the Zynq Processing system IP block and the AXI GPIO block. Then run the automation to connect it all together.<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">create_bd_design \"blink_1\"\nupdate_compile_order -fileset sources_1\nstartgroup\ncreate_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0\nendgroup\napply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external \"FIXED_IO, DDR\" apply_board_preset \"1\" Master \"Disable\" Slave \"Disable\" }  [get_bd_cells processing_system7_0]\nstartgroup\ncreate_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0\nendgroup<\/pre>\n\n\n\n<p>Now connect the DDR and the IO ports.<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">startgroup\napply_bd_automation -rule xilinx.com:bd_rule:board -config { Board_Interface {btns_4bits ( 4 Buttons ) } Manual_Source {Auto}}  [get_bd_intf_pins axi_gpio_0\/GPIO]\napply_bd_automation -rule xilinx.com:bd_rule:axi4 -config { Clk_master {Auto} Clk_slave {Auto} Clk_xbar {Auto} Master {\/processing_system7_0\/M_AXI_GP0} Slave {\/axi_gpio_0\/S_AXI} ddr_seg {Auto} intc_ip {New AXI Interconnect} master_apm {0}}  [get_bd_intf_pins axi_gpio_0\/S_AXI]\nendgroup\nregenerate_bd_layout\n\nstartgroup\nset_property -dict [list CONFIG.C_GPIO2_WIDTH {4} CONFIG.C_IS_DUAL {1} CONFIG.C_ALL_INPUTS {0} CONFIG.C_ALL_INPUTS_2 {1} CONFIG.GPIO_BOARD_INTERFACE {leds_4bits} CONFIG.GPIO2_BOARD_INTERFACE {btns_4bits} CONFIG.C_ALL_OUTPUTS {1}] [get_bd_cells axi_gpio_0]\nendgroup\napply_bd_automation -rule xilinx.com:bd_rule:board -config { Board_Interface {btns_4bits ( 4 Buttons ) } Manual_Source {Auto}}  [get_bd_intf_pins axi_gpio_0\/GPIO2]\n\nset_property name leds_4bits [get_bd_intf_ports btns_4bits]\napply_bd_automation -rule xilinx.com:bd_rule:board -config { Board_Interface {btns_4bits ( 4 Buttons ) } Manual_Source {Auto}}  [get_bd_intf_pins axi_gpio_0\/GPIO2]\n\n<\/pre>\n\n\n\n<p>Once you have run this, you should end up with a block diagram that looks something like the following.<\/p>\n\n\n\n<figure class=\"wp-block-image alignnone\"><a href=\"https:\/\/nuclearrambo.com\/wordpress\/programming-the-zynq-7000-with-vivado-2019-2-and-vitis\/bd\/\" rel=\"attachment wp-att-6721\"><img loading=\"lazy\" decoding=\"async\" width=\"1189\" height=\"502\" src=\"https:\/\/nuclearrambo.com\/wordpress\/wp-content\/uploads\/2020\/04\/bd.png\" alt=\"zynq vitis \" class=\"wp-image-6721\"\/><\/a><figcaption class=\"wp-element-caption\">AXI GPIO connected to the Zynq Processing system.<\/figcaption><\/figure>\n\n\n\n<center><p><script type=\"text\/javascript\">\n\tatOptions = {\n\t\t'key' : 'a488f095e80c8a74746e5fdca977eaea',\n\t\t'format' : 'iframe',\n\t\t'height' : 90,\n\t\t'width' : 728,\n\t\t'params' : {}\n\t};\n\tdocument.write('<scr' + 'ipt type=\"text\/javascript\" src=\"http' + (location.protocol === 'https:' ? 's' : '') + ':\/\/www.profitabledisplaynetwork.com\/a488f095e80c8a74746e5fdca977eaea\/invoke.js\"><\/scr' + 'ipt>');\n<\/script><\/p><\/center>\n\n\n\n<h2 class=\"wp-block-heading\">The configurations<\/h2>\n\n\n\n<p>Now, we need to configure various things in the block design. If you are using one of the standard development boards, things would be quite simple. In case you are using a custom board, you will need to manually set a lot of things. In my case, I am using a Zybo Z7010 board which has 4 gpio pins set as output and 4 as input. The moment I added the AXI GPIO block, it automatically assigned it to those pins.<\/p>\n\n\n\n<figure class=\"wp-block-image alignnone\"><a href=\"https:\/\/nuclearrambo.com\/wordpress\/programming-the-zynq-7000-with-vivado-2019-2-and-vitis\/gpio_axi\/\" rel=\"attachment wp-att-6722\"><img loading=\"lazy\" decoding=\"async\" width=\"976\" height=\"750\" src=\"https:\/\/nuclearrambo.com\/wordpress\/wp-content\/uploads\/2020\/04\/gpio_axi.png\" alt=\"Zybo vitis design\" class=\"wp-image-6722\"\/><\/a><figcaption class=\"wp-element-caption\">AXI GPIO settings<\/figcaption><\/figure>\n\n\n\n<p>If you are using a custom\/non-standard board, the board interface setting should be set to &#8220;Custom&#8221;. Next, switch to the IP Configuration tab and set everything manually.<\/p>\n\n\n\n<figure class=\"wp-block-image alignnone\"><a href=\"https:\/\/nuclearrambo.com\/wordpress\/programming-the-zynq-7000-with-vivado-2019-2-and-vitis\/manual-axi-gpio\/\" rel=\"attachment wp-att-6723\"><img loading=\"lazy\" decoding=\"async\" width=\"976\" height=\"832\" src=\"https:\/\/nuclearrambo.com\/wordpress\/wp-content\/uploads\/2020\/04\/manual-axi-gpio.jpg\" alt=\"zynq vitis zybo\" class=\"wp-image-6723\"\/><\/a><figcaption class=\"wp-element-caption\">AXI GPIO manual settings<\/figcaption><\/figure>\n\n\n\n<p>If you wish to set the system clock, you can double click on the Processing system block and do so.<\/p>\n\n\n\n<p>We cannot forget mapping the GPIO signals to the hardware pins. That is done through the constraints file. If you are using a standard board, you can simply place the given constraints file and un-comment the necessary pins.<\/p>\n\n\n\n<figure class=\"wp-block-image alignnone\"><a href=\"https:\/\/nuclearrambo.com\/wordpress\/programming-the-zynq-7000-with-vivado-2019-2-and-vitis\/constraints\/\" rel=\"attachment wp-att-6724\"><img loading=\"lazy\" decoding=\"async\" width=\"1920\" height=\"1080\" src=\"https:\/\/nuclearrambo.com\/wordpress\/wp-content\/uploads\/2020\/04\/constraints.jpg\" alt=\"\" class=\"wp-image-6724\"\/><\/a><figcaption class=\"wp-element-caption\">Set the constraints<\/figcaption><\/figure>\n\n\n\n<p>Observe carefully, the part where it says &#8220;[get_ports { led[0] }]&#8221;. The signal &#8220;led&#8221; is the name of our GPIO port in the block design. If you happen to make a mismatch in this naming, your signals will never see the real world. Make the settings in the port properties area as shown below.<\/p>\n\n\n\n<figure class=\"wp-block-image alignnone\"><a href=\"https:\/\/nuclearrambo.com\/wordpress\/programming-the-zynq-7000-with-vivado-2019-2-and-vitis\/port-properties\/\" rel=\"attachment wp-att-6725\"><img loading=\"lazy\" decoding=\"async\" width=\"1920\" height=\"1080\" src=\"https:\/\/nuclearrambo.com\/wordpress\/wp-content\/uploads\/2020\/04\/port-properties.jpg\" alt=\"Vivado block design port to pin map properties\" class=\"wp-image-6725\"\/><\/a><figcaption class=\"wp-element-caption\">Vivado block design port properties<\/figcaption><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\">Synthesis<\/h2>\n\n\n\n<p>Looking at the screenshots you may be wondering, where did the blinky_1_wrapper come from? Until now, you should only see the block design and nothing more. Now, right click on the block design and press &#8220;Generate output products&#8221;. Once that is done, right click again and press &#8220;Create HDL wrapper&#8221;. Finally, your project space should look similar to mine in the screenshots.<\/p>\n\n\n\n<p>Go the bottom and press &#8220;Generate bit stream&#8221;. This will initiate the synthesis and implementation process. When the bit stream generation, go to &#8220;<strong>File &gt; Export &gt; Export hardware<\/strong>&#8221; and make sure to &#8220;<strong>Include bit stream<\/strong>&#8220;. Our job with Vivado is done here. We now move to the Xilinx Vitis IDE to configure the rest.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Vitis IDE to program the Zynq processing system<\/h2>\n\n\n\n<p>Start your Vitis IDE and import the <strong>.xsa <\/strong>file that got generated when we exported the hardware from Vivado. To do this, do the follwing: <strong>&#8220;File &gt; New application project&#8221;. <\/strong>Make sure your project name has no spaces.<\/p>\n\n\n\n<p>Click on &#8220;<strong>Create a new platform from hardware (XSA)&#8221;<\/strong> and then press the &#8220;<strong>+<\/strong>&#8221; icon to import the hardware file we generated in Vivado.<\/p>\n\n\n\n<figure class=\"wp-block-image alignnone\"><a href=\"https:\/\/nuclearrambo.com\/wordpress\/programming-the-zynq-7000-with-vivado-2019-2-and-vitis\/vitis_import_vivado\/\" rel=\"attachment wp-att-6727\"><img loading=\"lazy\" decoding=\"async\" width=\"877\" height=\"921\" src=\"https:\/\/nuclearrambo.com\/wordpress\/wp-content\/uploads\/2020\/04\/vitis_import_vivado.jpg\" alt=\"import hardware in vitis\" class=\"wp-image-6727\"\/><\/a><figcaption class=\"wp-element-caption\">Import hardware XSA file in Vitis<\/figcaption><\/figure>\n\n\n\n<p>Proceeding further, select &#8220;Hello world&#8221; or an empty application project. Doing so, we will have two projects created in Vitis IDE. One project is the board support package that contains all the required drivers and definitions. The other project is our application project that will be building on top of the provided BSP.<\/p>\n\n\n\n<figure class=\"wp-block-image alignnone\"><a href=\"https:\/\/nuclearrambo.com\/wordpress\/programming-the-zynq-7000-with-vivado-2019-2-and-vitis\/vitis_import_vivado_imported_bsp\/\" rel=\"attachment wp-att-6728\"><img loading=\"lazy\" decoding=\"async\" width=\"237\" height=\"74\" src=\"https:\/\/nuclearrambo.com\/wordpress\/wp-content\/uploads\/2020\/04\/vitis_import_vivado_imported_bsp.jpg\" alt=\"imported vitis projects\" class=\"wp-image-6728\"\/><\/a><figcaption class=\"wp-element-caption\">BSP and the application project in Vitis IDE<\/figcaption><\/figure>\n\n\n\n<p>Expand the blink1_system project and open the &#8220;helloworld.c&#8221; file. Our aim here is to simply make use of the GPIO peripheral we just created in Vivado and toggle some LEDs.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Some C programming<\/h2>\n\n\n\n<p>There are two places where you can see the base address of our GPIO block. One is by looking at the properties of the GPIO block in the Vivado design and the other place is looking at the <strong>platform.spr <\/strong>file in Vitis IDE.<\/p>\n\n\n\n<figure class=\"wp-block-image alignnone\"><a href=\"https:\/\/nuclearrambo.com\/wordpress\/programming-the-zynq-7000-with-vivado-2019-2-and-vitis\/base_address_vitis\/\" rel=\"attachment wp-att-6729\"><img loading=\"lazy\" decoding=\"async\" width=\"1240\" height=\"799\" src=\"https:\/\/nuclearrambo.com\/wordpress\/wp-content\/uploads\/2020\/04\/base_Address_vitis.jpg\" alt=\"vitis ide peripheral address\" class=\"wp-image-6729\"\/><\/a><figcaption class=\"wp-element-caption\">Base address of our peripheral<\/figcaption><\/figure>\n\n\n\n<p>In order to send data over AXI, Xilinx provides us with <strong>Xil_in<\/strong> and <strong>Xil_out <\/strong>functions. We can either use those or go for the <strong>XGpio <\/strong>functions defined in the <strong>xgpio.h <\/strong>file.<\/p>\n\n\n\n<p>Two main functions will help us write to the GPIO peripheral. Firstly, let us initialize a GPIO instance by using the function XGpio_Initialize which takes two arguements. One of the arguments being the instance pointer and the other is device ID. You will find the device ID in <strong>xparameters.h<\/strong> file.<\/p>\n\n\n\n<p>We then set the direction of the GPIO using XGpio_SetDataDirection.<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">XGpio gpio;\n\nXGpio_Initialize(&amp;gpio, XPAR_GPIO_0_DEVICE_ID);\nXGpio_SetDataDirection(&amp;gpio, 1, 0x00000000); \/\/ set LED GPIO channel tristates to All Output\nXGpio_SetDataDirection(&amp;gpio, 2, 0xFFFFFFFF); \/\/ set BTN GPIO channel tristates to All Input<\/pre>\n\n\n\n<p>Remeber, that we have 4 output pins to drive. All of them are connected to a single GPIO channel called &#8220;GPIO&#8221; and &#8220;GPIO2&#8221;. If you don&#8217;t remember, go back to Vivado and check it out.<\/p>\n\n\n\n<p>The address to access each channel is fixed. So how do we drive individual LED pins? By setting individual bits in the output register.<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">#define BIT0\t0x01\n#define BIT1\t0x02\n#define BIT2\t0x04\n#define BIT3\t0x08<\/pre>\n\n\n\n<p>Now, let us drive these leds and see if that works.<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">XGpio_DiscreteWrite(&amp;gpio, 2, BIT0);\nusleep(100000);\nXGpio_DiscreteWrite(&amp;gpio, 2, BIT1);\nusleep(100000);\nXGpio_DiscreteWrite(&amp;gpio, 2, BIT2);\nusleep(100000);\nXGpio_DiscreteWrite(&amp;gpio, 2, BIT3);\nusleep(100000);<\/pre>\n\n\n\n<p>We are almost done. Click on the debug icon and create a debug configuration. Finally, build your code and debug\/Run. You should see dancing LEDs on your board.<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">#include &lt;stdio.h&gt;\n#include \"platform.h\"\n#include \"xil_printf.h\"\n#include \"xgpio.h\"\n#include \"xil_io.h\"\n#include \"sleep.h\"\n#define GPIO_BASE 0x41200000;\n\nXGpio gpio;\n\n#define BIT0\t0x01\n#define BIT1\t0x02\n#define BIT2\t0x04\n#define BIT3\t0x08\n\nint main()\n{\n        init_platform();\n        XGpio gpio;\n\tu32 btn, led;\n\tXGpio_Initialize(&amp;gpio, XPAR_GPIO_0_DEVICE_ID);\n\tXGpio_SetDataDirection(&amp;gpio, 1, 0x00000000); \/\/ set LED GPIO channel tristates to All Output\n\tXGpio_SetDataDirection(&amp;gpio, 2, 0xFFFFFFFF); \/\/ set BTN GPIO channel tristates to All Input\n\twhile (1)\n\t{\n\t\tXGpio_DiscreteWrite(&amp;gpio, 1, BIT0);\n\t\tusleep(100000);\n\t\tXGpio_DiscreteWrite(&amp;gpio, 1, BIT1);\n\t\tusleep(100000);\n\t\tXGpio_DiscreteWrite(&amp;gpio, 1, BIT2);\n\t\tusleep(100000);\n\t\tXGpio_DiscreteWrite(&amp;gpio, 1, BIT3);\n\t\tusleep(100000);\n\t\t\/\/xil_printf(\"\\rbutton state: %08x\", btn);\n\t\tprint(\"Hello World\\n\\r\");\n\t}\n\tcleanup_platform();\n\treturn 0;\n<\/pre>\n\n\n\n<center><script type=\"text\/javascript\"><br \/>\n\tatOptions = {<br \/>\n\t\t'key' : 'a488f095e80c8a74746e5fdca977eaea',<br \/>\n\t\t'format' : 'iframe',<br \/>\n\t\t'height' : 90,<br \/>\n\t\t'width' : 728,<br \/>\n\t\t'params' : {}<br \/>\n\t};<br \/>\n\tdocument.write('<scr' + 'ipt type=\"text\/javascript\" src=\"http' + (location.protocol === 'https:' ? 's' : '') + ':\/\/www.profitabledisplaynetwork.com\/a488f095e80c8a74746e5fdca977eaea\/invoke.js\"><\/scr' + 'ipt>');<br \/>\n<\/script><\/center>\n","protected":false},"excerpt":{"rendered":"<p>I purchased a Zynq 7000 development board recently and wanted to play with it for quite some time now. Finally, the lock-down due to the corona virus pandemic gave me some time to put&#46;&#46;&#46;<\/p>\n","protected":false},"author":1,"featured_media":6721,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1212,1562],"tags":[1750,170,1746,1747,1748,1749,1745],"class_list":["post-6720","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-electronics-2","category-tutorials","tag-digital-design","tag-electronics","tag-fpga","tag-vitis","tag-vivado","tag-xilinx","tag-zynq"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v20.5 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Programming the Zynq 7000 with Vivado 2019.2 and Vitis<\/title>\n<meta name=\"description\" content=\"Zynq 7 series completely changed the way modern systems are designed. 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